Viswa Ravichandran

GPU Microarchitecture

CUDA Register Mapping: From PTX to SASS

Introduction Register allocation is one of the critical aspects of GPU programming. On CPUs, the hardware’s “out-of-order” execution engine hides inefficiencies through register renaming, dynamically managing hundreds of physical registers behind 16 visible ones(General Purpose Registers). GPUs work differently: the per-thread register footprint chosen by the compiler becomes a real occupancy resource, with no CPU-style dynamic register renaming safety net.

GPU Microarchitecture

CUDA PTX: Learning to Read NVIDIA's Virtual ISA

TL;DR PTX is not the real hardware ISA. It is NVIDIA’s virtual instruction set that sits between CUDA C++ and SASS. PTX is the best layer for learning how the compiler thinks about types, addresses, predicates, and memory spaces. SASS is where architecture-specific details appear: actual opcodes, scheduling metadata, scoreboard behavior, and pipeline usage. If you can read PTX, you can usually answer: what computation is happening, what memory space it touches, and why the compiler generated a certain structure. If you want to optimize the last 20%, you eventually need to correlate PTX with SASS and measured hardware behavior. CPU Baseline: Why GPUs Need a Virtual ISA Layer On CPUs, most people think in terms of:

CUDA Kernel Programming

Memory Latency Hiding in CUDA using Streams

I’m starting a new CUDA project to deepen my understanding of GPU acceleration. I’ll begin with simple tasks like vector addition and move on to more involved projects, including image processing and language model optimizations. While this series won’t be a step-by-step tutorial, I’ll share the interesting parts of my implementations, highlighting the challenges I faced and the reasoning behind my decisions. For the complete code, feel free to check out the project repository.

InferX

Inference engine in the making. Exploring GPU kernels in different backend, and performance optimization through hands-on implementations.